This application claims the priority of Korean Patent Application No. 02-44676, filed Jul. 29, 2002, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated herein by reference.
1. Field of the Invention
The present invention generally relates to a clock distribution network, and more particularly, to a grid clock distribution network capable of distributing clock signals to a semiconductor integrated circuit (IC) chip through a grid distribution network.
2. Description of the Related Art
A clock distribution network is typically a circuit network through which clock signals may be transmitted to devices arranged on a semiconductor chip. It is desirable to maintain the phase relationship of the clock signals transmitted to the devices. In particular, it may be beneficial if the clock signals have substantially the same phase. However, because the devices may be positioned at different distances from clocking drivers, and/or the devices may have unique loading characteristics, received clock signals may differ in phase. That is, the clock signals may not reach each of the devices in a substantially simultaneous manner, thereby possibly causing the undesirable phase offset. This clock signal phase difference is generally referred to as clock skew.
Clock skew may limit reduction of a clock cycle time. If the clock skew is large, the operating speed and performance of a semiconductor chip may be reduced. Thus, it may be desirable to reduce possible clock skew over a large region of a semiconductor chip.
A grid clock distribution network may provide a clock signal(s) having substantially constant clock skew over a large region of a semiconductor chip. Initial design of the grid clock distribution network is relatively uncomplicated. Such a the grid clock distribution network may be used in semiconductor chips that operate at high speeds, such as high-speed microprocessors.
Grid clock distribution networks may have some difficulty effectively managing undesirable clock skew between an outer boundary and a center of a semiconductor chip. That is, clock skew may occur based upon a location within the semiconductor to which clock signals are transmitted.
FIG. 1 illustrates a conventional grid clock distribution network. Referring to FIG. 1, the conventional grid clock distribution network may include a plurality of clock drivers 120 arranged in a vicinity of a chip region 110 and a distribution network 130. The plurality of clock drivers 120 may receive and output clock signals. The distribution network 130 may be arranged in an x-direction and a y-direction of the chip region 110, and clock signals output from the clock drivers 120 may be transmitted to devices of the chip region 110 through the distribution network 130. Here, the clock drivers 120 of the conventional grid clock distribution network have substantially the same size regardless of their location. That is, the clock drivers 120, which have substantially the same driving capacity, may be arranged in the vicinity of the chip region 110 at substantially the same interval. The clock drivers 120 are capable of supplying clock signals through the distribution network 130.
In the case of the above structure, an area A1 of FIG. 1 is a relatively short distance from the clock drivers 120. Therefore, clock signals generated by the clock drivers 120 are capable of reaching an area A1 in a relatively short timeframe. However, an area A2 of FIG. 1, which is substantially a center of the chip region 110, is relatively far from the clock drivers 120 as compared to the proximity of the area A1. Accordingly, a timeframe for clock signals transmitted from the clock drivers 120 to reach the area A2 may be greater than a timeframe needed for clock signals to be transmitted from the clock drivers 120 to reach the area A1. Therefore, clock skew may occur between the areas A1 and A2.